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Address Translation in Paging and Why Page Size Is Usually a Power of Two

Address Translation in Paging and Why Page Size Is Usually a Power of Two

Verified Sources
May 27, 2026

Paging is a memory management scheme in which a process's virtual address space is divided into fixed-size pages and physical memory is divided into equally sized frames. The central idea of address translation is simple: the CPU generates a virtual address, the hardware separates it into a virtual page number and a page offset, then replaces the virtual page number with a physical frame number while leaving the offset unchanged.2

If the page size is 2n2^n bytes, then the low-order nn bits of the address are the offset, and the remaining high-order bits form the page number.2 For example, with a 32-bit virtual address and 4 KiB pages, the page size is 2122^{12} bytes, so:

Virtual Address=VPN∥Offset\text{Virtual Address} = \text{VPN} \parallel \text{Offset}

with 20 bits of VPN and 12 bits of offset.2

This bit-level decomposition is what makes paging efficient in hardware. The MMU can extract fields with simple shifting and masking, consult the page table, and construct the final physical address.2

Footnotes

  1. CS 450 Operating Systems Paging and TLB - Yue Duan - Lecture slides explaining VPN/offset splitting, TLBs, page faults, and multilevel paging. ↩ ↩2 ↩3

  2. Memory Management – Address Translation for Paging - Temple CIS - Slides describing page number/offset fields, power-of-two page sizes, and paging hardware. ↩ ↩2 ↩3

  3. Paging - UMass lecture notes mirror - Notes showing that power-of-two page sizes let addresses be partitioned cleanly into page number and offset. ↩

  4. How is Virtual Memory Translated to Physical Memory? - VMware - Practical explanation of TLB hit, TLB miss, and page table lookup behavior. ↩

Virtual Memory: Address Translation Example Walkthrough

Core Translation Rule

Paging changes the page number, not the offset. The offset names a byte within a page, and because pages and frames have the same size, that byte position is preserved exactly during translation.2

Footnotes

  1. CS 450 Operating Systems Paging and TLB - Yue Duan - Lecture slides explaining VPN/offset splitting, TLBs, page faults, and multilevel paging. ↩

  2. Memory Management – Address Translation for Paging - Temple CIS - Slides describing page number/offset fields, power-of-two page sizes, and paging hardware. ↩

The basic address translation mechanism

Suppose a process issues a virtual address AA. For a page size of SS, the translation conceptually computes:

VPN=⌊AS⌋,Offset=A mod S\text{VPN} = \left\lfloor \frac{A}{S} \right\rfloor,\qquad \text{Offset} = A \bmod S

Then the system looks up the VPN in the page table to obtain the page frame number or PFN. Finally:

Physical Address=PFN×S+Offset\text{Physical Address} = \text{PFN} \times S + \text{Offset}

This formulation is standard in paging descriptions, though real hardware usually avoids division and modulo by using bit fields when SS is a power of two.2

Each page table entry typically stores more than a frame number. It also includes control bits such as valid/present, protection permissions, dirty, and referenced/accessed bits. If the page is not present in memory, the MMU triggers a page fault, and the operating system loads the page from secondary storage before resuming execution.2

A crucial optimization is the TLB. Since consulting a page table in memory adds extra memory accesses, processors cache recent translations in the TLB. On a TLB hit, translation is fast; on a TLB miss, hardware or the OS must consult the page table, then often insert the mapping into the TLB for future use.3

Footnotes

  1. Paging - UMass lecture notes mirror - Notes showing that power-of-two page sizes let addresses be partitioned cleanly into page number and offset. ↩

  2. Powers of two - NJIT notes - Formal arithmetic explanation of mapping an address into page number and offset and why powers of two simplify this. ↩

  3. How is Virtual Memory Translated to Physical Memory? - VMware - Practical explanation of TLB hit, TLB miss, and page table lookup behavior. ↩ ↩2 ↩3

  4. CS 450 Operating Systems Paging and TLB - Yue Duan - Lecture slides explaining VPN/offset splitting, TLBs, page faults, and multilevel paging. ↩ ↩2

  5. Translation lookaside buffer - Wikipedia - Overview of TLB purpose, caching behavior, and support for multiple page sizes in modern processors. ↩

Virtual-to-Physical Translation Walkthrough

  1. 1
    Step 1

    The CPU issues an address as part of an instruction fetch, load, or store. That address belongs to the process's virtual address space, not directly to RAM.2

    Footnotes

    1. CS 450 Operating Systems Paging and TLB - Yue Duan - Lecture slides explaining VPN/offset splitting, TLBs, page faults, and multilevel paging. ↩

    2. How is Virtual Memory Translated to Physical Memory? - VMware - Practical explanation of TLB hit, TLB miss, and page table lookup behavior. ↩

  2. 2
    Step 2

    The MMU separates the high-order bits as the virtual page number and the low-order bits as the offset within the page. With a 4 KiB page, the offset occupies 12 bits because 4096=2124096 = 2^{12}.2

    Footnotes

    1. CS 450 Operating Systems Paging and TLB - Yue Duan - Lecture slides explaining VPN/offset splitting, TLBs, page faults, and multilevel paging. ↩

    2. Memory Management – Address Translation for Paging - Temple CIS - Slides describing page number/offset fields, power-of-two page sizes, and paging hardware. ↩

  3. 3
    Step 3

    The MMU first checks whether a recent translation for that VPN is cached. If so, the frame number is obtained immediately, avoiding a slower page-table memory access.3

    Footnotes

    1. CS 450 Operating Systems Paging and TLB - Yue Duan - Lecture slides explaining VPN/offset splitting, TLBs, page faults, and multilevel paging. ↩

    2. How is Virtual Memory Translated to Physical Memory? - VMware - Practical explanation of TLB hit, TLB miss, and page table lookup behavior. ↩

    3. Translation lookaside buffer - Wikipedia - Overview of TLB purpose, caching behavior, and support for multiple page sizes in modern processors. ↩

  4. 4
    Step 4

    If the TLB does not contain the translation, the system reads the page table entry from memory. In multilevel paging, this may require multiple lookups through page-directory structures.2

    Footnotes

    1. CS 450 Operating Systems Paging and TLB - Yue Duan - Lecture slides explaining VPN/offset splitting, TLBs, page faults, and multilevel paging. ↩

    2. Memory Management – Address Translation for Paging - Temple CIS - Slides describing page number/offset fields, power-of-two page sizes, and paging hardware. ↩

  5. 5
    Step 5

    The entry is examined to determine whether the page is present and whether the attempted access is allowed. If not present, a page fault occurs; if access is disallowed, a protection fault occurs.

    Footnotes

    1. How is Virtual Memory Translated to Physical Memory? - VMware - Practical explanation of TLB hit, TLB miss, and page table lookup behavior. ↩

  6. 6
    Step 6

    The physical frame number replaces the virtual page number, while the offset bits remain unchanged. The resulting physical address identifies the exact byte in RAM.2

    Footnotes

    1. CS 450 Operating Systems Paging and TLB - Yue Duan - Lecture slides explaining VPN/offset splitting, TLBs, page faults, and multilevel paging. ↩

    2. Memory Management – Address Translation for Paging - Temple CIS - Slides describing page number/offset fields, power-of-two page sizes, and paging hardware. ↩

  7. 7
    Step 7

    After a successful miss handling, the translation is typically cached in the TLB so later references to the same page can be translated faster.2

    Footnotes

    1. How is Virtual Memory Translated to Physical Memory? - VMware - Practical explanation of TLB hit, TLB miss, and page table lookup behavior. ↩

    2. Translation lookaside buffer - Wikipedia - Overview of TLB purpose, caching behavior, and support for multiple page sizes in modern processors. ↩

Worked example

Consider a 32-bit virtual address space with 4 KiB pages. Since 4 KiB=4096=2124\text{ KiB} = 4096 = 2^{12}, the offset uses 12 bits and the VPN uses 32−12=2032 - 12 = 20 bits.2

Let the virtual address be:

0x000011440x00001144

Then:

  • VPN = 0x000010x00001
  • Offset = 0x1440x144

If the page table entry for VPN 11 contains PFN 0x09AAF0x09AAF, then the physical address becomes:

Physical Address=0x09AAF∥0x144=0x09AAF144\text{Physical Address} = 0x09AAF \parallel 0x144 = 0x09AAF144

The essential observation is that only the page number changes; the offset 0x1440x144 is copied unchanged into the physical address.

This invariance exists because every frame is exactly the same size as every page. Byte 324 of a virtual page must map to byte 324 of the corresponding physical frame.2

Footnotes

  1. CS 450 Operating Systems Paging and TLB - Yue Duan - Lecture slides explaining VPN/offset splitting, TLBs, page faults, and multilevel paging. ↩ ↩2

  2. Memory Management – Address Translation for Paging - Temple CIS - Slides describing page number/offset fields, power-of-two page sizes, and paging hardware. ↩

  3. Paging - UMass lecture notes mirror - Notes showing that power-of-two page sizes let addresses be partitioned cleanly into page number and offset. ↩ ↩2

Bit Allocation in a 32-bit Virtual Address

Comparison of VPN and offset bits for common power-of-two page sizes

Why TLB Misses Matter

Without a TLB hit, paging can require extra memory references just to discover where the actual data lives. Multilevel page tables increase scalability, but they can also increase translation cost on a miss.3

Footnotes

  1. CS 450 Operating Systems Paging and TLB - Yue Duan - Lecture slides explaining VPN/offset splitting, TLBs, page faults, and multilevel paging. ↩

  2. Memory Management – Address Translation for Paging - Temple CIS - Slides describing page number/offset fields, power-of-two page sizes, and paging hardware. ↩

  3. Translation lookaside buffer - Wikipedia - Overview of TLB purpose, caching behavior, and support for multiple page sizes in modern processors. ↩

Why page size is normally a power of two

The main reason is hardware simplicity and speed. If page size is 2n2^n, then:

  • the offset is exactly the low-order nn bits,
  • the VPN is exactly the remaining high-order bits,
  • extracting both requires only bit masking and shifting, not general division or modulo.3

Mathematically, if S=2nS = 2^n, then for any address AA:

A=(VPN×2n)+OffsetA = (\text{VPN} \times 2^n) + \text{Offset}

where:

Offset=A  &  (2n−1),VPN=A≫n\text{Offset} = A \;\&\; (2^n - 1), \qquad \text{VPN} = A \gg n

This is far cheaper in digital hardware than implementing arbitrary division on every memory reference.2

Power-of-two page sizes also align naturally with binary-addressed memory systems. Since computers represent addresses in binary, powers of two create clean field boundaries in the address word. This makes page tables, TLBs, caches, and alignment rules easier to implement and reason about.2

Another benefit is that page-aligned structures are easier to organize. Page tables and sub-tables in multilevel schemes are commonly sized and aligned so indices cleanly select entries based on fixed groups of address bits. That regularity is one reason operating systems and CPU architectures standardize on page sizes such as 4 KiB, 2 MiB, and 1 GiB.

However, page size is a trade-off. Larger pages can reduce page-table size and increase TLB reach, but they may worsen internal fragmentation because the last page of an allocation may be only partly used.2

Footnotes

  1. Memory Management – Address Translation for Paging - Temple CIS - Slides describing page number/offset fields, power-of-two page sizes, and paging hardware. ↩ ↩2 ↩3 ↩4

  2. Paging - UMass lecture notes mirror - Notes showing that power-of-two page sizes let addresses be partitioned cleanly into page number and offset. ↩

  3. Powers of two - NJIT notes - Formal arithmetic explanation of mapping an address into page number and offset and why powers of two simplify this. ↩ ↩2

  4. How is Virtual Memory Translated to Physical Memory? - VMware - Practical explanation of TLB hit, TLB miss, and page table lookup behavior. ↩

  5. Translation lookaside buffer - Wikipedia - Overview of TLB purpose, caching behavior, and support for multiple page sizes in modern processors. ↩ ↩2

  6. CS 450 Operating Systems Paging and TLB - disadvantages section - Notes discussing internal fragmentation and page-size trade-offs. ↩

Common Questions and Subtleties

Lifecycle of a Memory Reference Under Paging

CPU issues virtual address

Stage 1

An instruction fetch or data access generates a virtual address in the process address space."

Footnotes

  1. CS 450 Operating Systems Paging and TLB - Yue Duan - Lecture slides explaining VPN/offset splitting, TLBs, page faults, and multilevel paging. ↩

MMU separates fields

Stage 2

The address is divided into a virtual page number and a page offset according to the page size.2"

Footnotes

  1. Memory Management – Address Translation for Paging - Temple CIS - Slides describing page number/offset fields, power-of-two page sizes, and paging hardware. ↩

  2. Paging - UMass lecture notes mirror - Notes showing that power-of-two page sizes let addresses be partitioned cleanly into page number and offset. ↩

TLB lookup

Stage 3

A fast associative lookup checks whether the page translation is already cached.2"

Footnotes

  1. How is Virtual Memory Translated to Physical Memory? - VMware - Practical explanation of TLB hit, TLB miss, and page table lookup behavior. ↩

  2. Translation lookaside buffer - Wikipedia - Overview of TLB purpose, caching behavior, and support for multiple page sizes in modern processors. ↩

Page table walk or hit resolution

Stage 4

On a hit, the PFN is available immediately; on a miss, the page table is consulted, possibly through multiple levels.2"

Footnotes

  1. CS 450 Operating Systems Paging and TLB - Yue Duan - Lecture slides explaining VPN/offset splitting, TLBs, page faults, and multilevel paging. ↩

  2. Memory Management – Address Translation for Paging - Temple CIS - Slides describing page number/offset fields, power-of-two page sizes, and paging hardware. ↩

Fault handling if needed

Stage 5

If the entry is invalid or not present, the processor traps into the OS, which services the page fault.2"

Footnotes

  1. CS 450 Operating Systems Paging and TLB - Yue Duan - Lecture slides explaining VPN/offset splitting, TLBs, page faults, and multilevel paging. ↩

  2. How is Virtual Memory Translated to Physical Memory? - VMware - Practical explanation of TLB hit, TLB miss, and page table lookup behavior. ↩

Physical address formation

Stage 6

The PFN is concatenated with the original offset and memory is accessed.2"

Footnotes

  1. CS 450 Operating Systems Paging and TLB - Yue Duan - Lecture slides explaining VPN/offset splitting, TLBs, page faults, and multilevel paging. ↩

  2. Paging - UMass lecture notes mirror - Notes showing that power-of-two page sizes let addresses be partitioned cleanly into page number and offset. ↩

For page size 2n2^n, the address splits naturally into two bit-fields. The low nn bits are the offset, and the remaining bits are the VPN. Translation becomes: PA=(PFN<<n)  ∣  Offset\text{PA} = (\text{PFN} << n) \; | \; \text{Offset} This is why power-of-two page sizes are so attractive in hardware.2

Footnotes

  1. Memory Management – Address Translation for Paging - Temple CIS - Slides describing page number/offset fields, power-of-two page sizes, and paging hardware. ↩

  2. Powers of two - NJIT notes - Formal arithmetic explanation of mapping an address into page number and offset and why powers of two simplify this. ↩

Summary of the answer

The paging address translation mechanism divides a virtual address into a page number and an offset, uses the page number to locate the mapped physical frame, and then forms the physical address by combining the frame number with the unchanged offset.3 A TLB accelerates this process by caching recent translations, while page faults handle references to pages not currently resident in RAM.3

Page sizes are normally powers of two because this lets hardware identify the offset and page number with simple bit operations instead of costly arithmetic. It also aligns cleanly with binary memory addressing, simplifies MMU and page-table design, and supports efficient implementations of TLBs and multilevel paging.3

Footnotes

  1. CS 450 Operating Systems Paging and TLB - Yue Duan - Lecture slides explaining VPN/offset splitting, TLBs, page faults, and multilevel paging. ↩ ↩2

  2. Memory Management – Address Translation for Paging - Temple CIS - Slides describing page number/offset fields, power-of-two page sizes, and paging hardware. ↩ ↩2

  3. Paging - UMass lecture notes mirror - Notes showing that power-of-two page sizes let addresses be partitioned cleanly into page number and offset. ↩ ↩2

  4. How is Virtual Memory Translated to Physical Memory? - VMware - Practical explanation of TLB hit, TLB miss, and page table lookup behavior. ↩

  5. Translation lookaside buffer - Wikipedia - Overview of TLB purpose, caching behavior, and support for multiple page sizes in modern processors. ↩

  6. Powers of two - NJIT notes - Formal arithmetic explanation of mapping an address into page number and offset and why powers of two simplify this. ↩

Knowledge Check

Question 1 of 4
Q1Single choice

In paging, which part of a virtual address remains unchanged when forming the physical address?

Explore Related Topics

1

Understanding Belady's Anomaly in Operating Systems

Belady's Anomaly shows that, for some page‑replacement policies, adding more physical frames can increase the number of page faults.

  • FIFO (a non‑stack algorithm) does not satisfy the inclusion property and can exhibit the anomaly.
  • On the reference string 1,2,3,4,1,2,5,1,2,3,4,51,2,3,4,1,2,5,1,2,3,4,5, FIFO yields 99 faults with 33 frames but 1010 faults with 44 frames.
  • Stack algorithms such as LRU or Optimal obey M(N,t)⊆M(N+1,t)M(N,t)\subseteq M(N+1,t), guaranteeing that more frames never raise fault counts.
  • Designing a virtual‑memory system with stack‑based replacement eliminates Belady's Anomaly.
2

Purpose of the Modify Bit in a Page Table

The modify (dirty) bit in a page‑table entry signals whether a page in RAM has been altered since it was loaded from its backing store, guiding the OS during page replacement.

  • If the bit is 0 the page is clean and can be discarded; if 1 it is dirty and must be written back before the frame is reused.
  • Hardware (or the MMU) sets the bit automatically on any write to the page.
  • Eviction cost:
    Eviction cost={read replacement page only,modify=0write old page+read replacement page,modify=1\text{Eviction cost}= \begin{cases}\text{read replacement page only}, & \text{modify}=0\\ \text{write old page} + \text{read replacement page}, & \text{modify}=1\end{cases}
  • It works with other status bits (present, accessed) to support efficient replacement policies and avoid unnecessary disk I/O.
3

Page Replacement Analysis: FIFO vs LRU for a 4-Frame Reference String

The page‑replacement analysis compares FIFO and LRU for the reference string 1,3,4,4,3,2,1,7,5,6,4,2,1,21,3,4,4,3,2,1,7,5,6,4,2,1,2 using four frames, showing that LRU incurs fewer faults.

  • FIFO simulation results in 1010 page faults.
  • LRU simulation results in 99 page faults.
  • LRU is superior here because it evicts the least recently used page, better exploiting temporal locality.
  • FIFO evicts the oldest loaded page, which can discard recently used pages and lead to higher fault rates.
  • This example illustrates why LRU often outperforms FIFO, though FIFO’s simplicity can cause anomalies such as Belady’s.
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