TCP/IP Networking: The Architecture of the Internet

Packets are the fundamental data units used in network communication, operating at the OSI Network layer and enabling packet‑switching across diverse paths.

• A packet consists of a header (source/destination IP, TTL, etc.), payload (user data), and often a trailer for error checking (e.g., CRC).
• Encapsulation adds headers at each OSI layer (segment → packet → frame) and decapsulation removes them at the receiver.
• Packets are routed by IP addresses via routers’ routing tables, while frames use MAC addresses for local hop‑to‑hop delivery.
• Exceeding the MTU causes fragmentation, and tools like Wireshark can sniff packets for debugging.

A computer network is a packet‑switched system that interconnects devices to exchange data using layered protocols such as OSI/TCP‑IP, enabling addressing, routing, and a range of services across different scopes.

• Core concepts: encapsulation/decapsulation, bandwidth, latency, with transfer time ≈ $\frac{\text{Data Size}}{\text{Bandwidth}}+\text{Latency}$ and throughput ≤ $\min(\text{Access Link Rate},\text{Path Bottleneck Rate})$.
• OSI (7 layers) and TCP/IP (4 layers) models map functions from physical signaling up to application protocols (e.g., HTTP, DNS).
• Addressing hierarchy: MAC for local delivery, IP for routing, DNS for name resolution, DHCP for automatic configuration, and NAT for private‑public translation.
• Transport choices: TCP provides reliable, ordered delivery with congestion control; UDP offers low‑overhead, best‑effort delivery for latency‑sensitive apps.
• Security fundamentals include firewalls, VPNs, TLS, and access controls, which must be balanced against performance and usability.

The course explains the essential structures and mechanisms of operating systems, covering kernel designs, process control, memory management, and CPU scheduling.

• Kernels are either monolithic (all services in one privileged space) or microkernel (minimal core with services in user space).
• Processes follow a five‑state lifecycle (new, ready, running, waiting, terminated) and a context switch saves the current PCB, runs the scheduler, and restores the next process.
• Virtual memory uses paging, an MMU, and page tables; a missing page triggers a page fault to load data from secondary storage.
• Scheduling algorithms such as Round Robin (time‑quantum preemptive) and Shortest Job First (optimizes average wait time but can starve long jobs) manage CPU allocation.
• Exceeding physical memory causes thrashing, where excessive paging degrades system responsiveness.